1. Field of the Invention
The present invention relates to an integrated circuit having a programmable logic array implemented in complementary (e.g. CMOS) technology.
2. Description of the Prior Art
A programmable logic array (PLA) implements a desired logical truth table by accepting a plurality of logical input signals and decoding them to provide a plurality of output signals. The decoding function is usually accomplished using two arrays of logic gates, referred to as the "AND" plane and the "OR" plane. The input signals are applied to the AND plane, which partially decodes them, and applies the intermediate results as inputs to the OR plane. The terms AND and OR are representative of the Boolean algebra operations that are typically performed in the respective arrays. However, electrically both of the arrays are usually similar, and comprise a series of signal line conductors whose voltage state represents the logical value of a given logic output term (OR plane), or intermediate result (AND plane).
The signal line conductors in both the AND and OR planes are precharged to a high voltage state in the case of a dynamic PLA. In the case of static PLA, they are connected to a load device that tends to continuously pull them up to a high voltage state. In either case, logic transistors are connected in a desired parallel pattern between the signal lines and a reference voltage (e.g., ground). Then, in order to perform a decoding operation, the input signals (or intermediate results) are applied to the control terminals of the logic transistors. If any of the logic transistors connected to a given signal line is thereby placed in the conductive state, that signal line is pulled down to the ground voltage state. Hence, electrically both the AND and OR planes perform a "NOR" operation.
The dynamic PLA design provides for low current consumption, since no dc current flows through the conductive logic transistors during a decode operation. However, clocks are required to switch between the precharge and decode operations for the AND and OR planes in a dynamic PLA. A first clock is applied to the AND plane, and a second clock delayed relative to the first is applied to the OR plane, so that the AND plane has sufficient time to complete its decode operation prior to performing the decode in the OR plane. The delay between the clocks must be sufficiently long to ensure that no erroneous discharge of a conductor occurs in the OR plane, since once discharged there is no further precharge signal available, and an erroneous output results. A disadvantage of using two clocks is that the circuit required for the clock signals does not readily fit in the area of either the AND or the OR plane, so that it is placed externally thereto. This complicates the layout of the integrated circuit, especially when computer aided design techniques that utilize geometrically regular blocks of circuitry are used.
It is known to use a static array for both the AND and OR planes, instead of a dynamic array. The static array eliminates the need for any clocks, since both planes are receptive to decode input signals whenever they arrive. However, a static array draws dc current whenever any of the logic transistors is in the "on" (i.e., conducting) state, and hence the power consumption is undesirably high for some applications.
It is therefore desirable to obtain a programmable logic array that obtains low power consumption and ease of layout.